STMicroelectronics STM32F05 series - Figure 239. USART Example of Synchronous Transmission; Figure 240. USART Data Clock Timing Diagram (M=0)

RM0091 Universal synchronous asynchronous receiver transmitter (USART)
Doc ID 018940 Rev 1 595/742
Figure 239. USART example of synchronous transmission
Figure 240. USART data clock timing diagram (M=0)
RX
TX
SCLK
USART
Data out
Data in
Synchronous device
Clock
(e.g. slave SPI)
M=0 (8 data bits)
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
Clock (CPOL=1, CPHA=1)
Start LSB
MSB Stop
* LBCL bit controls last data clock pulse
Start
Idle or preceding
transmission
Data on TX
Stop
Clock (CPOL=0, CPHA=0)
01 23456 7
*
*
*
*
Idle or next
transmission
*
Capture Strobe
LSB
MSB
Data on RX
01 23456 7
(from master)
(from slave)