Analog-to-digital converter (ADC) RM0091
182/742 Doc ID 018940 Rev 1
Figure 29. Single conversions of a sequence, hardware trigger
1. EXTSEL=TRGx (over-frequencied), EXTEN=0x1 (rising edge), CONT=0
2. CHSEL=0xF, SCANDIR=0, AUTDLY=0, AUTOFF=0
Figure 30. Continuous conversions of a sequence, hardware trigger
1. EXTSEL=TRGx, EXTEN=0x2 (falling edge), CONT=1
2. CHSEL=0xF, SCANDIR=0, AUTDLY=0, AUTOFF=0
RDY
ADSTART
(1)
EOC
EOSEQ
ADC state
(2)
CH0
by S/W by H/W
CH1 CH1CH2 CH3 CH0RDY CH2 CH3
RDY
ADC_DR
D0 D1 D2 D3 D0 D1 D2 D3
TRGx
(1)
triggered ignored
RDY CH0 CH1 CH2 CH3
D0 D1 D2
CH0 CH1 CH2 CH3 CH0
D3 D0 D1 D2 D3
STOP RDY
ADSTART
(1)
EOC
EOSEQ
ADC state
(2)
ADC_DR
TRGx
(1)
ADSTP
by S/W by H/W
triggered ignored