STMicroelectronics STM32F05 series User Manual

RM0091 Interrupts and events
Doc ID 018940 Rev 1 163/742
11.3 EXTI registers
Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).
11.3.1 Interrupt mask register (EXTI_IMR)
Address offset: 0x00
Reset value: 0x0F94 0000 (See note below)
Note: The reset value for the internal lines (18, 20, 23, 24, 25, 26 and 27) is set to ‘1’ in order to
enable the interrupt by default.
11.3.2 Event mask register (EXTI_EMR)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. MR27 MR26 MR25 MR24 MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:28 Reserved, must be kept at reset value (0).
Bits 27:0 MRx: Interrupt Mask on external/internal line x
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. MR27 MR26 MR25 MR24 MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:28 Reserved, must be kept at reset value (0).
Bits 27:0 MRx: Event mask on external/internal line x
0: Event request from Line x is masked
1: Event request from Line x is not masked

STMicroelectronics STM32F05 series Specifications

General

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English