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RM0091 Inter-integrated circuit (I

C) interface

Doc ID 018940 Rev 1 529/742

Bit 10 OVR: Overrun/Underrun (slave mode)

This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun

error occurs. It is cleared by software by setting the OVRCF bit.

Note: This bit is cleared by hardware when PE=0 or SWRST is set.

Bit 9 ARLO: Arbitration lost

This flag is set by hardware when the interface in case of arbitration loss. It is cleared by

software by setting the ARLOCF bit.

Note: This bit is cleared by hardware when PE=0 or SWRST is set.

Bit 8 BERR: Bus error

This flag is set by hardware when a misplaced Start or Stop condition is detected. It is

cleared by software by setting BERRCF bit.

Note: This bit is cleared by hardware when PE=0 or SWRST is set.

Bits 7 TCR: Transfer Complete Reload

This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is

cleared by software when NBYTES is written to a non-zero value.

Note: This bit is cleared by hardware when PE=0 or SWRST is set.

This flag is only for master mode, or for slave mode when the SBC bit is set.

Bit 6 TC: Transfer Complete (master mode)

This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been

transferred. It is cleared by software when START bit or STOP bit is set.

Note: This bit is cleared by hardware when PE=0 or SWRST is set.

Bit 5 STOPF: Stop detection flag

This flag is set by hardware when a Stop condition is detected on the bus and the peripheral

is involved in this transfer:

– either as a master, provided that the STOP condition is generated by the peripheral.

– or as a slave, provided that the peripheral has been addressed previously during this

transfer.

It is cleared by software by setting the STOPCF bit.

Note: This bit is cleared by hardware when PE=0 or SWRST is set.

Bit 4 NACKF: Not Acknowledge received flag

This flag is set by hardware when a NACK is received after a byte transmission. It is cleared

by software by setting the NACKCF bit.

Note: This bit is cleared by hardware when PE=0 or SWRST is set.

Bit 3 ADDR: Address matched (slave mode)

This bit is set by hardware as soon as the received slave address matched with one of the

enabled slave addresses. It is cleared by software by setting ADDRCF bit.

Note: This bit is cleared by hardware when PE=0 or SWRST is set.

STMicroelectronics STM32F05 series User Manual

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