Universal synchronous asynchronous receiver transmitter (USART) RM0091
574/742 Doc ID 018940 Rev 1
Through these pins, serial data is transmitted and received in normal USART mode as
frames comprising:
● An Idle Line prior to transmission or reception
● A start bit
● A data word (8 or 9 bits) least significant bit first
● 1, 1.5, 2 Stop bits indicating that the frame is complete
● This interface uses a baud rate generator - with a 12-bit mantissa and 4-bit fraction
● A status register (USART_ISR)
● Receive and transmit data registers (USART_RDR, USART_TDR)
● A baud rate register (USART_BRR) - 12-bit mantissa and 4-bit fraction.
● A guardtime register (USART_GTPR) in case of Smartcard mode.
Refer to Section 25.7: USART registers on page 611 for the definitions of each bit.
The following pin is required to interface in synchronous mode and Smartcard mode:
● SCLK: Clock output. This pin outputs the transmitter data clock for synchronous
transmission corresponding to SPI master mode (no clock pulses on start bit and stop
bit, and a software option to send a clock pulse on the last data bit). In parallel, data
can be received synchronously on RX. This can be used to control peripherals that
have shift registers (e.g. LCD drivers). The clock phase and polarity are software
programmable. In Smartcard mode, SCLK output can provide the clock to the
Smartcard.
The following pins are required in Hardware flow control mode:
● nCTS: Clear To Send blocks the data transmission at the end of the current transfer
when high
● nRTS: Request to send indicates that the USART is ready to receive data (when low).
The following pin is required in RS485 Hardware control mode:
● DE: Driver Enable activates the transmission mode of the external transceiver.
Note: DE and nRTS share the same pin.
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