Universal synchronous asynchronous receiver transmitter (USART) RM0091
620/742 Doc ID 018940 Rev 1
Bit 9 CTSE: CTS enable
0: CTS hardware flow control disabled
1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0).
If the nCTS input is deasserted while data is being transmitted, then the transmission is
completed before stopping. If data is written into the data register while nCTS is asserted,
the transmission is postponed until nCTS is asserted.
This bit can only be written when the USART is disabled (UE=0)
Note: If the hardware flow control feature is not supported, this bit is reserved and forced by
hardware to ‘0’. Please refer to Section 25.4: USART implementation on page 573.
Bit 8 RTSE: RTS enable
0: RTS hardware flow control disabled
1: RTS output enabled, data is only requested when there is space in the receive buffer. The
transmission of data is expected to cease after the current character has been transmitted.
The nRTS output is asserted (pulled to 0) when data can be received.
This bit can only be written when the USART is disabled (UE=0).
Note: If the hardware flow control feature is not supported, this bit is reserved and forced by
hardware to ‘0’. Please refer to Section 25.4: USART implementation on page 573.
Bit 7 DMAT: DMA enable transmitter
This bit is set/reset by software
1: DMA mode is enabled for transmission
0: DMA mode is disabled for transmission
Note: If the USART does not support DMA, this bit is reserved and forced by hardware to ‘0’.
Please refer to Section 25.4: USART implementation on page 573.
Bit 6 DMAR: DMA enable receiver
This bit is set/reset by software
1: DMA mode is enabled for reception
0: DMA mode is disabled for reception
Note: If the USART does not support DMA, this bit is reserved and forced by hardware to ‘0’.
Please refer to Section 25.4: USART implementation on page 573.
Bit 5 SCEN: Smartcard mode enable
This bit is used for enabling Smartcard mode.
0: Smartcard Mode disabled
1: Smartcard Mode enabled
This bit field can only be written when the USART is disabled (UE=0).
Note: If the USART does not support Smartcard mode, this bit is reserved and forced by
hardware to ‘0’. Please refer to Section 25.4: USART implementation on page 573.
Bit 4 NACK: Smartcard NACK enable
0: NACK transmission in case of parity error is disabled
1: NACK transmission during parity error is enabled
This bit field can only be written when the USART is disabled (UE=0).
Note: If the USART does not support Smartcard mode, this bit is reserved and forced by
hardware to ‘0’. Please refer to Section 25.4: USART implementation on page 573.
Bit 3 HDSEL: Half-duplex selection
Selection of Single-wire Half-duplex mode
0: Half duplex mode is not selected
1: Half duplex mode is selected
This bit can only be written when the USART is disabled (UE=0).
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