Freescale Semiconductor MPC5553 - Page 1006

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 22-21
22.3.3.8 Interrupt Masks Low Register (CANx_IMRL)
CANx_IMRL allows enabling or disabling any number of a range of 32 message buffer interrupts. It
contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an
interrupt after a successful transmission or reception (that is, when the corresponding IFRL bit is set).
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RBUF
63M
BUF
62M
BUF
61M
BUF
60M
BUF
59M
BUF
58M
BUF
57M
BUF
56M
BUF
55M
BUF
54M
BUF
53M
BUF
52M
BUF
51M
BUF
50M
BUF
49M
BUF
48M
W
Reset0000000000000000
Reg Addr
Base + 0x0024
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RBUF
47M
BUF
46M
BUF
45M
BUF
44M
BUF
43M
BUF
42M
BUF
41M
BUF
40M
BUF
39M
BUF
38M
BUF
37M
BUF
36M
BUF
35M
BUF
34M
BUF
33M
BUF
32M
W
Reset0000000000000000
Reg Addr
Base + 0x0024
Figure 22-9. Interrupt Masks High Register (CANx_IMRH)
Table 22-12. CANx_IMRH Field Descriptions
Bits Name Description
0–31 BUFnM Message buffer n mask. Enables or disables the respective FlexCAN2 message buffer
(MB63 to MB32) Interrupt.
0 The corresponding buffer Interrupt is disabled
1 The corresponding buffer Interrupt is enabled
Note: Setting or clearing a bit in the IMRH register can assert or negate an interrupt
request, respectively.
0123456789101112131415
RBUF
31M
BUF
30M
BUF
29M
BUF
28M
BUF
27M
BUF
26M
BUF
25M
BUF
24M
BUF
23M
BUF
22M
BUF
21M
BUF
20M
BUF
19M
BUF
18M
BUF
17M
BUF
16M
W
Reset0000000000000000
Reg Addr Base + 0x0028
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RBUF
15M
BUF
14M
BUF
13M
BUF
12M
BUF
11M
BUF
10M
BUF
09M
BUF
08M
BUF
07M
BUF
06M
BUF
05M
BUF
04M
BUF
03M
BUF
02M
BUF
01M
BUF
00M
W
Reset0000000000000000
Reg Addr Base + 0x0028
Figure 22-10. Interrupt Mask Low Register (CANx_IMRL)