MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
22-20 Freescale Semiconductor
22.3.3.7 Interrupt Masks High Register (ICANx_IMRH)
CANx_IMRH allows any number of a range of 32 message buffer interrupts to be enabled or disabled. It
contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an
interrupt after a successful transmission or reception (that is, when the corresponding IFRH bit is set).
22 TXWRN TX error counter. This status bit indicates that repetitive errors are occurring during
message transmission.
0 No such occurrence
1 TXECTR 96
23 RXWRN RX error counter. This status bit indicates when repetitive errors are occurring during
messages reception.
0 No such occurrence
1 RXECTR 96
24 IDLE CAN bus IDLE state. This status bit indicates when CAN bus is in IDLE state.
0 No such occurrence
1 CAN bus is now IDLE
25 TXRX Current FlexCAN2 status (transmitting/receiving). This status bit indicates if FlexCAN2 is
transmitting or receiving a message when the CAN bus is not in IDLE state. This bit has
no meaning when IDLE is asserted.
0 FlexCAN2 is receiving a message (IDLE = 0)
1 FlexCAN2 is transmitting a message (IDLE = 0)
26–27 FLTCONF
[0:1]
Fault confinement state. This status bit indicates the confinement state of the FlexCAN2
module. If the LOM bit in the CANx_CR is asserted, the FLTCONF field will indicate “Error
Passive”. Because the CANx_CR is not affected by soft reset, the FLTCONF field will not
be affected by soft reset if the LOM bit is asserted.
00 Error active
01 Error passive
1X Bus off
28 — Reserved.
29 BOFFINT Bus off interrupt. This status bit is set when FlexCAN2 is in the bus off state. If
CANx_CR[BOFFMSK] is set, an interrupt is generated to the CPU. This bit is cleared by
writing it to 1. Writing 0 has no effect.
0 No such occurrence
1 FlexCAN2 module is in ‘Bus Off’ state
30 ERRINT Error interrupt. This status bit indicates that at least one of the error bits (bits 16-21) is set.
If CANx_CR[ERRMSK] is set, an interrupt is generated to the CPU. This bit is cleared by
writing it to 1. Writing 0 has no effect.
0 No such occurrence
1 Indicates setting of any error bit in the CANx_ESR
31 — Reserved.
Table 22-11. CANx_ESR Field Descriptions (Continued)
Bits Name Description
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