Freescale Semiconductor MPC5553 - Page 1096

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 25-57
25.11.13.3 DTM Operation
25.11.13.3.1 DTM Queueing
NZ6C3 implements a message queue for DTM messages. Messages that enter the queue are transmitted
via the auxiliary pins in the order in which they are queued.
NOTE
If multiple trace messages need to be queued at the same time, watchpoint
messages will have the highest priority (WPM  OTM  BTM  DTM).
25.11.13.3.2 Relative Addressing
The relative address feature is compliant with the IEEE-ISTO 5001-2003 standard recommendations,
and is designed to reduce the number of bits transmitted for addresses of data trace messages. Refer to
Section 25.11.12.3.2, “ Relative Addressing for details.
25.11.13.3.3 Data Trace Windowing
Data write/read messages are enabled via the RWT1(2) field in the data trace control register (DTC) for
each DTM channel. Data trace windowing is achieved via the address range defined by the DTEA and
DTSA registers and by the RC1(2) field in the DTC. All e200z6 initiated read/write accesses which fall
inside or outside these address ranges, as programmed, are candidates to be traced.
25.11.13.3.4 Data Access/Instruction Access Data Tracing
The Nexus3 module is capable of tracing both instruction access data or data access data. Each trace
window can be configured for either type of data trace by setting the DI1(2) field within the data trace
control register for each DTM channel.
25.11.13.3.5 e200z6 Bus Cycle Special Cases
Collision Priority All messages have the following priority: WPM  OTM  BTM  DTM. A DTM
message which attempts to enter the queue at the same time as a watchpoint
message or ownership trace message or branch trace message will be lost. A
subsequent read/write will queue a data trace read/write with sync. message.
Table 25-37. e200z6 Bus Cycle Cases
Special Case Action
e200z6 bus cycle aborted Cycle ignored
e200z6 bus cycle with data error (TEA
) Data Trace Message discarded
e200z6 bus cycle completed without error Cycle captured & transmitted
e200z6 bus cycle initiated by NZ6C3 Cycle ignored
e200z6 bus cycle is an instruction fetch Cycle ignored
Table 25-36. Data Trace Exception Summary (Continued)
Exception Condition Exception Handling