MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 25-87
25.14.5.4 DTM Operation
25.14.5.4.1 Enabling Data Trace Messaging
Data trace messaging can be enabled in one of two ways.
• Setting the DC1[TM] field to enable data trace
• Using the WT[DTS] field to enable data trace on watchpoint hits
25.14.5.4.2 DTM Queueing
NXDM implements a programmable depth queue for queuing all messages. Messages that enter the queue
are transmitted via the auxiliary pins in the order in which they are queued.
NOTE
If multiple trace messages need to be queued at the same time, watchpoint
messages will have the highest priority (WPM -> DTM).
25.14.5.4.3 Relative Addressing
The relative address feature is compliant with IEEE-ISTO Nexus 5001-2003 and is designed to reduce
the number of bits transmitted for addresses of data trace messages. Relative addressing is the same as
described for the NZ6C3 in Section 25.11.12.3.2, “ Relative Addressing.”
25.14.5.4.4 Data Trace Windowing
Data write/read messages are enabled via the RWT1(2) field in the data trace control register (DTC) for
each DTM channel. Data trace windowing is achieved via the address range defined by the DTEA and
DTSA registers and by the RC1(2) field in the DTC. All eDMA initiated read/write accesses which fall
inside or outside these address ranges, as programmed, are candidates to be traced.
25.14.5.4.5 System Bus Cycle Special Cases
25.14.5.5 Data Trace Timing Diagrams (8 MDO configuration)
Data trace timing for the NXDM is the same as for the NZ6C3. See Section Section 25.11.13.4, “ Data
Trace Timing Diagrams (8 MDO Configuration).”
Table 25-59. System Bus Cycle Special Cases
Special Case Action
System bus cycle aborted (DABORT asserted) Cycle ignored
System bus cycle with data error Data Trace Message discarded
System bus cycle completed without error Cycle captured and transmitted
System bus cycle is an instruction fetch Cycle ignored
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