MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
25-86 Freescale Semiconductor
• Upon data trace write/read after the previous dtm message was lost due to an attempted access to
a secure memory location.
• Upon data trace write/read after the previous dtm message was lost due to a collision entering the
fifo between the dtm message and any of the following: error message, or watchpoint message.
Data Trace synchronization messages provide the full address (without leading zeros) and insure that
development tools fully synchronize with data trace regularly. Synchronization messages provide a
reference address for subsequent DTMs, in which only the unique portion of the data trace address is
transmitted. The format for data trace write/read w/ sync. Messages is as follows:
Figure 25-66. Data Write/Read w/ Sync Message Format
Exception conditions that result in data trace synchronization are summarized in Table 25-58., “Data Trace
Exception Summary.”
Table 25-58. Data Trace Exception Summary
Exception Condition Exception Handling
System Reset Negation At the negation of JTAG reset (JCOMP), queue pointers, counters, state
machines, and registers within the NXDM module are reset. If data trace is
enabled, the first data trace message is a data write/read w/ sync. message.
Data Trace Enabled The first data trace message (after data trace has been enabled) is a
synchronization message.
Exit from Low Power/Debug Upon exit from a low power mode or debug mode the next data trace
message will be converted to a data write/read w/ sync. message.
Queue Overrun An error message occurs when a new message cannot be queued due to
the message queue being full. The FIFO will discard messages until it has
completely emptied the queue. After it is emptied, an error message will be
queued. The error encoding will indicate which types of messages
attempted to be queued while the FIFO was being emptied. The next DTM
message in the queue will be a data write/read w/ sync. message.
Periodic Data Trace Synchronization A forced synchronization occurs periodically after 255 data trace messages
have been queued. A data write/read w/ sync. message is queued. The
periodic data trace message counter then resets.
Event In if the nexus module is enabled, an evti
assertion initiates a data trace
write/read w/ sync. message upon the next data write/read (if data trace is
enabled and the eic bits of the dc register have enabled this feature).
Attempted Access to Secure Memory Any attempted read or write to secure memory locations will temporarily
disable data trace & cause the corresponding DTM to be lost. A subsequent
read/write will queue a data trace read/write w/ sync. message.
Collision Priority All messages have the following priority: Error -> WPM -> DTM. A DTM
message which attempts to enter the queue at the same time as an error
message, or watchpoint message will be lost. A subsequent read/write will
queue a data trace read/write w/ sync. message.
DATA
msb lsb
234
F-ADDR DSZ SRC
5
4 bits
1
TCODE (001101 or 001110)
3 bits1-32 bits1-64 bits 6 bits
Max length = 109 bits; Min length = 15 bits
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