MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 3-21
Figure 3-13. e200z6 Unified Cache Block Diagram
3.3.2.1 Cache Organization
The e200z6 cache is organized as eight (MPC5554)/two (MPC5553) ways of 128 sets with each line
containing 32 bytes (four doublewords) plus parity of storage. Figure 3-14 illustrates the cache
organization, terminology used, the cache line format and cache tag formats.
Bus
Interface
Unit
Address/
Control
Cache
Control Logic
Tag Array
Data Array
Data Path
Processor
Core
Address Path
Control
Data
Address
Bus
Data
Control
Data
Memory
Unit
Address
System
Management
To Next Page
Loading...