MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
12-38 Freescale Semiconductor
Figure 12-23. Burst 32-bit Read Cycle, Zero Wait States
Figure 12-24. Burst 32-bit Read Cycle, One Initial Wait State
12.4.2.5.1 TBDIP Effect on Burst Transfer
Some memories require different timing on the BDIP signal than the default to run burst cycles. Using the
default value of TBDIP = 0 in the appropriate EBI base register results in BDIP being asserted (SCY+1)
cycles after the address transfer phase, and being held asserted throughout the cycle regardless of the wait
CLKOUT
ADDR[8:31]
BDIP
DATA[0:31]
TA
RD_WR
TSIZ[0:1]
TS
OE
CSx
Expects more data
ADDR[29:31] = ‘000’
‘00’
DATA is valid
Wait state
CLKOUT
ADDR[8:31]
BDIP
DATA[0:31]
TA
RD_WR
TSIZ[0:1]
TS
OE
CSx
Expects more data
ADDR[29:31] = ‘000’
DATA is valid
‘00’
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