Freescale Semiconductor MPC5553 - Page 513

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
12-64 Freescale Semiconductor
Figure 12-46. MCU Read followed by External Master Read to Different CS Bank
MCU starts read access
Receive bus busy
negated for 2nd cycle
External master and MCU off
Using the internal arbiter
External master starts read access
DATA is valid
Both masters off
RD_WR
TSIZ[0:1]
BDIP
BB
ADDR[8:31]
DATA[0:31]
TS
TA
CSy
OE
CLKOUT
BR (Input)
BG
DATA is valid
CSx