MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
13-30 Freescale Semiconductor
13.4.2.3.1 Software Locking
A software mechanism is provided to independently lock/unlock each high-, mid-, and low-address space
against program and erase.
Software locking is done through the FLASH_LMLR (low-/mid-address space block locking register),
FLASH_SLMLR (secondary low-/mid-address space block locking register), or FLASH_HLR
(high-address space block locking register). These can be written through register writes, and can be read
through register reads.
When the program/erase operations are enabled through hardware, software locks are enforced through
doing register writes.
13.4.2.3.2 Flash Program Suspend/Resume
The program sequence may be suspended to allow read access to the flash core. It is not possible to erase
or program during a program suspend. Interlock writes should not be attempted during program suspend.
A program suspend can be initiated by changing the value of the FLASH_MCR[PSUS] bit from a 0 to a
1. FLASH_MCR[PSUS] can be set high at any time when FLASH_MCR[PGM] and
FLASH_MCR[EHV] are high. A 0 to 1 transition of FLASH_MCR[PSUS] causes the flash module to start
the sequence to enter program suspend, which is a read state. The module is not suspended until
FLASH_MCR[DONE] = 1. At this time flash core reads may be attempted. After it is suspended, the flash
core may only be read. Reads to the blocks being programmed/erased return indeterminate data.
The program sequence is resumed by writing a logic 0 to FLASH_MCR[PSUS]. FLASH_MCR[EHV]
must be set to a 1 before clearing FLASH_MCR[PSUS] to resume operation. When the operation resumes,
the flash module continues the program sequence from one of a set of predefined points. This may extend
the time required for the program operation.
13.4.2.4 Flash Erase
Erase changes the value stored in all bits of the selected blocks to logic 1. Locked or disabled blocks cannot
be erased. If multiple blocks are selected for erase during an erase sequence, the blocks are erased
sequentially starting with the lowest numbered block and terminating with the highest. Aborting an erase
operation will leave the flash core blocks being erased in an indeterminate data state. This can be recovered
by executing an erase on the affected blocks.
The erase sequence consists of the following sequence of events:
1. Change the value in the FLASH_MCR[ERS] bit from 0 to a 1.
2. Select the block, or blocks to be erased by writing ones to the appropriate registers in
FLASH_LMSR or FLASH_HSR. If the shadow row is to be erased, this step may be skipped, and
FLASH_LMSR and FLASH_HSR are ignored. For shadow row erase, see section
Section 13.4.2.5, “Flash Shadow Block” for more information.
NOTE
Lock and Select are independent. If a block is selected and locked, no erase
will occur. See Section 13.3.2.2, “Low-/Mid-Address Space Block Locking
Register (FLASH_LMLR), Section 13.3.2.3, “High-Address Space Block
Locking Register (FLASH_HLR)” and Section 13.3.2.4, “Secondary
Low-/Mid-Address Space Block Locking Register (FLASH_SLMLR)” for
more information.
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