MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
17-54 Freescale Semiconductor
Figure 17-42. eMIOS OPWFMB Mode Example — A1 = 0 (0% Duty Cycle)
Figure 17-43 shows the timing for the A1 and B1 loading. A1 and B1 use the same signal to trigger a load,
which is generated based on the selected counter reaching one. This event is defined as the cycle boundary.
The load signal pulse has the duration of one system clock cycle and occurs at the first system clock period
of every cycle of the counter. If A2 and B2 are written within cycle (n), their values are loaded into A1 and
B1, respectively, at the first clock of cycle (n+1). The update disable bits, EMIOS_OUDR, can be used to
control the update of these registers, thus allowing the delay of A1 and B1 update for synchronization
purposes.
During the load pulse A1 still holds its old value, which is updated on the following system clock cycle.
During the A1 load pulse, an internal by-pass allows the use of A2 instead of A1 for matches if A2 is either
0 or 1, thus allowing matches to be generated even when A1 is being loaded. This approach allows a
uniform channel operation for any A2 value, including 1 and 0.
In Figure 17-43 it is assumed that the channel and global prescalers are set to one, meaning that the channel
internal counter transition at every system clock cycle. FLAGs can be generated only on B1 matches when
MODE[5] is cleared, or on both A1 and B1 matches when MODE[5] is set. Because B1 FLAG occurs at
the cycle boundary, this flag can be used to indicate that A2 or B2 data written on cycle (n) were loaded to
A1 or B1, respectively, thus generating matches in cycle (n+1).
1
4
5
A1 Value
0x000004
A1 Match
A1 Match Negative
Output Flip-Flop
Time
B1 Match Negative Edge Detect
B1 Match
B1 Match Negative
B1 Value 0x000008
System Clock
Prescaled Clock
A2 Value 0x000000
0x000000
A1 Match Positive
A1 Match Positive Edge Detect
No Transition at this Point
1
Cycle n Cycle n+1
Edge Detection
Edge Detection
Edge Detection
A1 Match
Negative
Edge Detect
EDPOL = 0
Write to A2
EMIOS_CCNTRn
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