Freescale Semiconductor MPC5553 - Page 775

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
19-20 Freescale Semiconductor
19.3.2.7 eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCRn)
The eQADC_IDCRs contain bits to enable the generation of interrupt or eDMA requests when the
corresponding flag bits are set in EQADC_FISRn (Section 19.3.2.8).
0123456789101112131415
RNCI
En
TORI
En
PIEn EOQI
En
CFUI
En
0CFF
En
CFF
Sn
0000RFOI
En
0RFD
En
RFD
Sn
W
Reset0000000000000000
Reg
Addr
EQADC_BASE+0x0060 (EQADC_IDCR0); EQADC_BASE+0x0062 (EQADC_IDCR1);
EQADC_BASE+0x0064 (EQADC_IDCR2) EQADC_BASE+0x0066 (EQADC_IDCR3);
EQADC_BASE+0x0068 (EQADC_IDCR4); EQADC_BASE+0x006A (EQADC_IDCR5)
Figure 19-8. eQADC Interrupt and eDMA Control Registers (EQADC_IDCRn)
Table 19-11. EQADC_IDCRn Field Descriptions
Bits Name Description
0NCIEn Non-coherency interrupt enable n. Enables the eQADC to generate an interrupt request
when the corresponding NCFn, described in Section 19.3.2.8, is asserted.
0 Disable non-coherency interrupt request
1 Enable non-coherency interrupt request
1 TORIEn Trigger overrun interrupt enable n. Enables the eQADC to generate an interrupt request
when the corresponding TORFn (described in Section 19.3.2.8) is asserted.
Apart from generating an independent interrupt request for a CFIFOn trigger overrun
event, the eQADC also provides a combined interrupt at which the result FIFO overflow
interrupt, the command FIFO underflow interrupt, and the command FIFO trigger overrun
interrupt requests of all CFIFOs are ORed. When RFOIEn, CFUIEn, and TORIEn are all
asserted, this combined interrupt request is asserted whenever one of the following 18
flags becomes asserted: RFOFn, CFUFn, and TORFn (assuming that all interrupts are
enabled). See Section 19.4.7, “eQADC eDMA/Interrupt Request
,” for details.
0 Disable trigger overrun interrupt request
1 Enable trigger overrun interrupt request
2PIEn Pause interrupt enable n. Enables the eQADC to generate an interrupt request when the
corresponding PFx in EQADC_FISRn (See Section 19.3.2.8
) is asserted.
0 Disable pause interrupt request
1 Enable pause interrupt request
3 EOQIEn End-of-queue interrupt enable n. Enables the eQADC to generate an interrupt request
when the corresponding EOQFn in EQADC_FISRn (See Section 19.3.2.8
) is asserted.
0 Disable end of queue interrupt request.
1 Enable end of queue interrupt request.
4CFUIEn CFIFO underflow interrupt enable n. Enables the eQADC to generate an interrupt request
when the corresponding CFUFn in EQADC_FISRn (See Section 19.3.2.8
) is asserted.
Apart from generating an independent interrupt request for a CFIFOn underflow event, the
eQADC also provides a combined interrupt at which the result FIFO overflow interrupt, the
command FIFO underflow interrupt, and the command FIFO trigger overrun interrupt
requests of all CFIFOs are ORed. When RFOIEn, CFUIEn, and TORIEn are all asserted,
this combined interrupt request is asserted whenever one of the following 18 flags
becomes asserted: RFOFn, CFUFn, and TORFn (assuming that all interrupts are
enabled). See Section 19.4.7, “eQADC eDMA/Interrupt Request,” for details.
0 Disable underflow interrupt request
1 Enable underflow interrupt request