MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 20-11
20.3.2.2 DSPI Transfer Count Register (DSPIx_TCR)
The DSPIx_TCR contains a counter that indicates the number of SPI transfers made. The transfer counter
is intended to assist in queue management. The user must not write to the DSPIx_TCR while the DSPI is
running.
20.3.2.3 DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn)
The MPC5553/MPC5554 DSPI modules each contain eight clock and transfer attribute registers
(DSPIx_CTARn) which are used to define different transfer attribute configurations. Each DSPIx_CTAR
controls:
•Frame size
• Baud rate and transfer delay values
• Clock phase
• Clock polarity
• MSB/LSB first
DSPIx_CTARs support compatibility with the QSPI module in the MPC5xx family of MCUs. See
Section 20.5.4, “MPC5xx QSPI Compatibility with the DSPI,” for a discussion on DSPI/QSPI
compatibility. At the initiation of an SPI or DSI transfer, control logic selects the DSPIx_CTAR that
contains the transfer’s attributes. The user must not write to the DSPIx_CTARs while the DSPI is running.
0123456789101112131415
R SPI_TCNT
W
Reset0000000000000000
Reg Addr Base + 0x0008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W
Reset0000000000000000
Reg Addr Base + 0x0008
Figure 20-4. DSPI Transfer Count Register (DSPIx_TCR)
Table 20-4. DSPIx_TCR Field Descriptions
Bits Name Description
0–15 SPI_TCNT
[0:15]
SPI transfer counter. Counts the number of SPI transfers the DSPI makes. The
SPI_TCNT field is incremented every time the last bit of an SPI frame is transmitted.
A value written to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to
zero at the beginning of the frame when the CTCNT field is set in the executing SPI
command. The transfer counter ‘wraps around,’ incrementing the counter past 65535
resets the counter to zero.
16–31 — Reserved.
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