MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 20-55
the idle state of the SCK. The clock phase bit selects if the data on SOUT is valid before or on the first
SCK edge.
When the DSPI is the bus slave, CPOL and CPHA bits in the DSPIx_CTAR0 (SPI slave mode) or
DSPIx_CTAR1 (DSI slave mode) select the polarity and phase of the serial clock. Even though the bus
slave does not control the SCK signal, clock polarity, clock phase and number of bits to transfer must be
identical for the master device and the slave device to ensure proper transmission.
The DSPI supports four different transfer formats:
• Classic SPI with CPHA = 0
• Classic SPI with CPHA = 1
• Modified transfer format with CPHA = 0
• Modified transfer format with CPHA = 1
A modified transfer format is supported to allow for high-speed communication with peripherals that
require longer setup times. The DSPI can sample the incoming data later than halfway through the cycle
to give the peripheral more setup time. The MTFE bit in the DSPIx_MCR selects between classic SPI
format and modified transfer format. The classic SPI formats are described in Section 20.4.7.1, “Classic
SPI Transfer Format (CPHA = 0)” and Section 20.4.7.2, “Classic SPI Transfer Format (CPHA = 1).” The
modified transfer formats are described in Section 20.4.7.3, “Modified SPI/DSI Transfer Format (MTFE
= 1, CPHA = 0)” and Section 20.4.7.4, “Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 1).”
In the SPI and DSI configurations, the DSPI provides the option of keeping the PCS signals asserted
between frames. See Section 20.4.7.5, “Continuous Selection Format” for details.
20.4.7.1 Classic SPI Transfer Format (CPHA = 0)
The transfer format shown in Figure 20-36 is used to communicate with peripheral SPI slave devices
where the first data bit is available on the first clock edge. In this format, the master and slave sample their
SIN pins on the odd-numbered SCK edges and change the data on their SOUT pins on the even-numbered
SCK edges.
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