STMicroelectronics STM32F05 series - Page 14

Contents RM0091
14/742 Doc ID 018940 Rev 1
18.5.6 TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . . . 408
18.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . . . . . 409
18.5.8 TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . . 412
18.5.9 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
18.5.10 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
18.5.11 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . . 415
18.5.12 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . . 416
18.5.13 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . . 416
18.5.14 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . . 417
18.5.15 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . . 417
18.5.16 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . . 419
18.5.17 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . . 420
18.5.18 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
18.6 TIM16 and TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
18.6.1 TIM16 and TIM17 control register 1 (TIM16_CR1 and TIM17_CR1) . 422
18.6.2 TIM16 and TIM17 control register 2 (TIM16_CR2 and TIM17_CR2) . 423
18.6.3 TIM16 and TIM17 DMA/interrupt enable register (TIM16_DIER and
TIM17_DIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
18.6.4 TIM16 and TIM17 status register (TIM16_SR and TIM17_SR) . . . . . . 425
18.6.5 TIM16 and TIM17 event generation register (TIM16_EGR and
TIM17_EGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
18.6.6 TIM16 and TIM17 capture/compare mode register 1 (TIM16_CCMR1 and
TIM17_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
18.6.7 TIM16 and TIM17 capture/compare enable register (TIM16_CCER and
TIM17_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
18.6.8 TIM16 and TIM17 counter (TIM16_CNT and TIM17_CNT) . . . . . . . . . 432
18.6.9 TIM16 and TIM17 prescaler (TIM16_PSC and TIM17_PSC) . . . . . . . 432
18.6.10 TIM16 and TIM17 auto-reload register (TIM16_ARR and TIM17_ARR) . .
432
18.6.11 TIM16 and TIM17 repetition counter register (TIM16_RCR and
TIM17_RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
18.6.12 TIM16 and TIM17 capture/compare register 1 (TIM16_CCR1 and
TIM17_CCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
18.6.13 TIM16 and TIM17 break and dead-time register (TIM16_BDTR and
TIM17_BDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
18.6.14 TIM16 and TIM17 DMA control register (TIM16_DCR and TIM17_DCR) .
436
18.6.15 TIM16 and TIM17 DMA address for full transfer (TIM16_DMAR and
TIM17_DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
18.6.16 TIM16 and TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438