System and memory overview RM0091
36/742 Doc ID 018940 Rev 1
DMA bus
This bus connects the AHB master interface of the DMA to the BusMatrix which manages
the access of CPU DCode and DMA to SRAM, Flash memory and peripherals.
BusMatrix
The BusMatrix manages the access arbitration between the core system bus and the DMA
master bus. The arbitration uses a Round Robin algorithm. The BusMatrix is composed of
two masters (CPU AHB, System bus) and four slaves (FLITF, SRAM, AHB2GPIO and
AHB2APB bridges).
AHB peripherals are connected on system bus through a BusMatrix to allow DMA access.
AHB2APB bridges (APB)
The AHB2APB bridges provide full synchronous connections between the AHB and the
APB bus.
Refer to Table 2.2.2 on page 37 for the address mapping of the peripherals connected to
this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF).
Before using a peripheral you have to enable its clock in the RCC_AHBENR,
RCC_APB2ENR or RCC_APB1ENR register.
Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
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