RM0091 Basic timer (TIM6)
Doc ID 018940 Rev 1 445/742
Figure 188. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded)
Figure 189. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)
00
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
01 02 03 04 05 06 0732 33 34 35 3631
Auto-reload register
FF 36
Write a new value in TIMx_ARR
CK_INT
00
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
01 02 03 04 05 06 07F1 F2 F3 F4 F5F0
Auto-reload preload register
F5 36
Auto-reload shadow register
F5 36
Write a new value in TIMx_ARR
CK_PSC
To Next Page
Loading...
