RM0091 Serial peripheral interface / inter-IC sound (SPI/I2S)
Doc ID 018940 Rev 1 671/742
Bit 9 SSM: Software slave management
When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.
0: Software slave management disabled
1: Software slave management enabled
Note: This bit is not used in I
2
S mode and SPI TI mode
Bit 8 SSI: Internal slave select
This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the
NSS pin and the IO value of the NSS pin is ignored.
Note: This bit is not used in I
2
S mode and SPI TI mode
Bit 7 LSBFIRST: Frame format
0: MSB transmitted first
1: LSB transmitted first
Note: 1. This bit should not be changed when communication is ongoing.
2. This bit is not used in I
2
S mode and SPI TI mode
Bit 6 SPE: SPI enable
0: Peripheral disabled
1: Peripheral enabled
Note: 1. This bit is not used in I
2
S mode.
2. When disabling the SPI, follow the procedure described in Procedure for disabling the
SPI on page 644.
Bits 5:3 BR[2:0]: Baud rate control
000: f
PCLK
/2
001: f
PCLK
/4
010: f
PCLK
/8
011: f
PCLK
/16
100: f
PCLK
/32
101: f
PCLK
/64
110: f
PCLK
/128
111: f
PCLK
/256
Note: These bits should not be changed when communication is ongoing.
This bit is not used in I
2
S mode.
Bit 2 MSTR: Master selection
0: Slave configuration
1: Master configuration
Note: 1. This bit should not be changed when communication is ongoing.
2. This bit is not used in I
2
S mode.
Bit1 CPOL: Clock polarity
0: CK to 0 when idle
1: CK to 1 when idle
Note: 1. This bit should not be changed when communication is ongoing.
2. This bit is not used in I
2
S mode and SPI TI mode
Bit 0 CPHA: Clock phase
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
Note: 1. This bit should not be changed when communication is ongoing.
2. This bit is not used in I
2
S mode and SPI TI mode
To Next Page
Loading...
Need help?
General
