Reset and clock control (RCC) RM0091
84/742 Doc ID 018940 Rev 1
The devices have the following additional clock sources:
● 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wakeup from Stop/Standby mode.
● 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-
time clock (RTCCLK)
● 14 MHz high speed internal RC (HSI14) dedicated for ADC.
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
Several prescalers can be used to configure the frequency of the AHB and the APB
domains. The AHB and the APB domains maximum frequency is 48 MHz.
The Cortex system timer is always clocked by the AHB clock divided by 8 or directly by the
AHB clock (through Cortex Systick configuration bits).
All the peripheral clocks are derived from their bus clock (HCLK or PCLK) except:
● The Flash memory programming interface clock (FLITFCLK) which is always the HSI
clock.
● The option byte loader clock which is always the HSI clock
● The ADC clock which is derived (selected by software) from one of the two following
sources:
– dedicated HSI14 clock, to run always at the maximum sampling rate
– APB clock (PCLK) divided by 2 or 4
● The USART1 clock which is derived (selected by software) from one of the four
following sources:
– system clock
–HSI clock
– LSE clock
– APB clock (PCLK)
● The I2C1 clock which is derived (selected by software) from one of the two following
sources:
– system clock
–HSI clock
● The CEC clock which is derived from the HSI clock divided by 244 or from the LSE
clock.
● The I2S1 clock which is always the system clock.
● The RTC clock which is derived from the LSE, LSI or from the HSE clock divided by 32.
● The IWWDG clock which is always the LSI clock.
The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or directly with the Cortex
clock (HCLK), configurable in the SysTick Control and Status Register.