RM0091 Reset and clock control (RCC)
Doc ID 018940 Rev 1 95/742
Bits 21:18 PLLMUL: PLL multiplication factor
These bits are written by software to define the PLL multiplication factor. These bits can be
written only when PLL is disabled.
Caution: The PLL output frequency must not exceed 48 MHz.
0000: PLL input clock x 2
0001: PLL input clock x 3
0010: PLL input clock x 4
0011: PLL input clock x 5
0100: PLL input clock x 6
0101: PLL input clock x 7
0110: PLL input clock x 8
0111: PLL input clock x 9
1000: PLL input clock x 10
1001: PLL input clock x 11
1010: PLL input clock x 12
1011: PLL input clock x 13
1100: PLL input clock x 14
1101: PLL input clock x 15
1110: PLL input clock x 16
1111: PLL input clock x 16
Bit 17 PLLXTPRE: HSE divider for PLL input clock
This bits is set and cleared by software to select the HSE division factor for the PLL. It can
be written only when the PLL is disabled.
Note: This bit is the same as the LSB of PREDIV in Clock configuration register 2
(RCC_CFGR2) (for compatibility with other STM32 products)
0000: HSE input to PLL not divided
0001: HSE input to PLL divided by 2
Bit 16 PLLSRC: PLL entry clock source
Set and cleared by software to select PLL clock source. This bit can be written only when
PLL is disabled.
0: HSI/2 selected as PLL input clock
1: HSE/PREDIV selected as PLL input clock (refer to Section 7.4.12: Clock configuration
register 2 (RCC_CFGR2) on page 113
Bit 15 Reserved, must be kept at reset value.
Bit 14 ADCPRE: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADC.
0: PCLK divided by 2
1: PCLK divided by 4
Bits 13:11 Reserved, must be kept at reset value.
Bits 10:8 PPRE: PCLK prescaler
Set and cleared by software to control the division factor of the APB clock (PCLK).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
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