STMicroelectronics STM32WL5 Series - Page 42

Contents RM0453
42/1450 RM0453 Rev 5
38.10.3 ITM trace privilege register (ITM_TPR) . . . . . . . . . . . . . . . . . . . . . . . 1388
38.10.4 ITM trace control register (ITM_TCR) . . . . . . . . . . . . . . . . . . . . . . . . 1389
38.10.5 ITM CoreSight peripheral identity register 4 (ITM_PIDR4) . . . . . . . . 1390
38.10.6 ITM CoreSight peripheral identity register 0 (ITM_PIDR0) . . . . . . . . 1390
38.10.7 ITM CoreSight peripheral identity register 1 (ITM_PIDR1) . . . . . . . . 1391
38.10.8 ITM CoreSight peripheral identity register 2 (ITM_PIDR2) . . . . . . . . 1391
38.10.9 ITM CoreSight peripheral identity register 3 (ITM_PIDR3) . . . . . . . . 1392
38.10.10 ITM CoreSight component identity register 0 (ITM_CIDR0) . . . . . . . 1392
38.10.11 ITM CoreSight peripheral identity register 1 (ITM_CIDR1) . . . . . . . . 1393
38.10.12 ITM CoreSight component identity register 2 (ITM_CIDR2) . . . . . . . 1393
38.10.13 ITM CoreSight component identity register 3 (ITM_CIDR3) . . . . . . . 1394
38.10.14 CPU1 ITM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394
38.11 CPU1 trace port interface unit (TPIU) . . . . . . . . . . . . . . . . . . . . . . . . . 1395
38.11.1 TPIU supported port size register (TPIU_SSPSR) . . . . . . . . . . . . . . 1396
38.11.2 TPIU current port size register (TPIU_CSPSR) . . . . . . . . . . . . . . . . . 1396
38.11.3 TPIU asynchronous clock prescaler register (TPIU_ACPR) . . . . . . . 1396
38.11.4 TPIU selected pin protocol register (TPIU_SPPR) . . . . . . . . . . . . . . 1397
38.11.5 TPIU formatter and flush status register (TPIU_FFSR) . . . . . . . . . . . 1397
38.11.6 TPIU formatter and flush control register (TPIU_FFCR) . . . . . . . . . . 1398
38.11.7 TPIU formatter synchronization counter register (TPIU_FSCR) . . . . 1399
38.11.8 TPIU claim tag set register (TPIU_CLAIMSETR) . . . . . . . . . . . . . . . 1399
38.11.9 TPIU claim tag clear register (TPIU_CLAIMCLR) . . . . . . . . . . . . . . . 1400
38.11.10 TPIU device configuration register (TPIU_DEVIDR) . . . . . . . . . . . . . 1400
38.11.11 TPIU device type identifier register (TPIU_DEVTYPER) . . . . . . . . . . 1401
38.11.12 TPIU CoreSight peripheral identity register 4 (TPIU_PIDR4) . . . . . . 1401
38.11.13 TPIU CoreSight peripheral identity register 0 (TPIU_PIDR0) . . . . . . 1402
38.11.14 TPIU CoreSight peripheral identity register 1 (TPIU_PIDR1) . . . . . . 1402
38.11.15 TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) . . . . . . 1403
38.11.16 TPIU CoreSight peripheral identity register 3 (TPIU_PIDR3) . . . . . . 1403
38.11.17 TPIU CoreSight component identity register 0 (TPIU_CIDR0) . . . . . 1404
38.11.18 TPIU CoreSight peripheral identity register 1 (TPIU_CIDR1) . . . . . . 1404
38.11.19 TPIU CoreSight component identity register 2 (TPIU_CIDR2) . . . . . 1405
38.11.20 TPIU CoreSight component identity register 3 (TPIU_CIDR3) . . . . . 1405
38.11.21 CPU 1 TPIU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405
38.12 Microcontroller debug unit (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . 1407
38.12.1 DBGMCU identity code register (DBGMCU_IDCODER) . . . . . . . . . . 1408
38.12.2 DBGMCU configuration register (DBGMCU_CR) . . . . . . . . . . . . . . . 1408