MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
25-16 Freescale Semiconductor
25.6.2.4 Port Configuration Register (PCR)
The PCR, shown in Figure 25-4, is used to select the NPC mode of operation, enable MCKO and select
the MCKO frequency, and enable or disable MCKO gating. This register should be configured as soon as
the NPC is enabled.
NOTE
The mode (MCKO_GT) or clock division (MCKO_DIV) bits must not be
modified after MCKO has been enabled. Changing the mode or clock
division while MCKO is enabled can produce unpredictable results.
11–1 MIC Manufacturer identity code. Contains the reduced Joint Electron Device Engineering
Council (JEDEC) ID for Freescale, 0xE.
0 — Fixed per JTAG 1149.1
1 Always set
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RFPMMCKO_
GT
MCKO_
EN
MCKO_DIV 000000000 0
W
Reset0 0 0 0 0 0 000000000 0
Reg Index 127
15 14 13 121110987654321 0
R0 0 0 0 0 0000000000
PSTAT
_EN
W
Reset0 0 0 0 0 0 000000000 0
Reg Index 127
Figure 25-4. Port Configuration Register (PCR)
Table 25-11. PCR Field Descriptions
Bits Name Description
31 FPM Full port mode. Determines if the auxiliary output port uses the full MDO port or a reduced
MDO port to transmit messages.
0 The subset of MDO[3:0] pins are used to transmit messages.
1 All MDO[11:0] pins are used to transmit messages.
30 MCKO_GT MCKO clock gating control. Enables or disables MCKO clock gating. If clock gating is
enabled, the MCKO clock is gated when the NPC is in enabled mode but not actively
transmitting messages on the auxiliary output port. When clock gating is disabled, MCKO
is allowed to run even if no auxiliary output port messages are being transmitted.
0 MCKO gating is disabled.
1 MCKO gating is enabled.
Table 25-10. DID Register Field Descriptions (Continued)
Bits Name Description
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