System Interface Unit (SIU)
MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
6-24 Freescale Semiconductor
6.3.1.12.4 MPC5554: Pad Configuration Registers 4–27 (SIU_PCR4–SIU_PCR27)
NOTE
The definitions and settings for PCR4 through PCR27 in the MPC5553
device differ from the MPC5554 definitions and settings. Refer to the
previous two sections for a description of the MPC5553 settings.
The SIU_PCR4–SIU_PCR27 registers control the pin function, direction, and static electrical attributes of
the ADDR[8:31]_GPIO[4:27] pins.
Figure 6-17. MPC5554: ADDR[8:31]_GPIO[4:27]
Pad Configuration Registers (SIU_PCR4–SIU_PCR27)
Refer to Table 6-16 for bit field definitions.
Address: Base + 0x0048 through Base + 0x0076 Access: Read / write[5:11, 14:15]
0123456789101112131415
R 00000
PA OBE
1
1
When configured as ADDR[12:31], the OBE bit has no effect. When configured as GPO, set the OBE bit to 1.
IBE
2
2
When configured as ADDR[12:31] or GPO, set the IBE bit to 1 to reflect the pin state in the corresponding GPDI register. Clear
the IBE to zero to reduce power consumption. When configured as GPI, set the IBE bit to 1.
DSC ODE
3
3
When configured as ADDR[12:31], clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
00
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as ADDR[12:31].
WPS
6
W
RESET: 000000001100001 1
Address: Base + 0x0048 through Base + 0x0076 Access: Read / write[5:11, 14:15]
0123456789101112131415
R 00000
PA
1
1
The PA fields in PCR0–3 and PCR4–7 must not be configured simultaneously to select ADDR[8:11] as an input. Only configure
one set of pins for address input.
OBE
2
2
When configured as ADDR[8:31], the OBE bit has no effect. When configured as GPO, set the OBE bit to 1.
IBE
3
3
When configured as ADDR[8:31] or GPO, set the IBE bit to 1 to reflect the pin state in the corresponding GPDI register. Clear
the IBE to 0 to reduce power consumption. When configured as GPI, set the IBE bit to 1.
DSC ODE
4
4
When configured as ADDR[8:31], clear the ODE bit to 0.
HYS
5
5
If external master operation is enabled, clear the HYS bit to 0.
00
WPE
6
6
Refer to the EBI section for weak pullup settings when configured as ADDR[8:31].
WPS
6
W
RESET: 000000001100001 1
To Next Page
Loading...