MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
9-14 Freescale Semiconductor
9.3.1.4 eDMA Enable Error Interrupt Registers (EDMA_EEIRH, EDMA_EEIRL)
The EDMA_EEIRH and EDMA_EEIRL provide a bit map for the 64 channels (32 in the MPC5553) to
enable the error interrupt signal for each channel. For the MPC5554, EDMA_EEIRH supports channels
63–32, while EDMA_EEIRL covers channels 31–00. For the MPC5553, EDMA_EEIRL maps to channels
31-0. EDMA_EEIRH is reserved on the MPC5553 and accessing it will result in a bus error.
The state of any given channel’s error interrupt enable is directly affected by writes to these registers; it is
also affected by writes to the EDMA_SEEIR and EDMA_CEEIR. The EDMA_SEEIR and
EDMA_CEEIR are provided so that the error interrupt enable for a single channel can easily be modified
without the need to perform a read-modify-write sequence to the EDMA_EEIRH and EDMA_EEIRL.
Both the DMA error indicator and this error interrupt enable flag must be asserted before an error interrupt
request for a given channel is asserted.
0123456789101112131415
R EEI63 EEI62 EEI61 EEI60 EEI59 EEI58 EEI57 EEI56 EEI55 EEI54 EEI53 EEI52 EEI51 EEI50 EEI49 EEI48
W
Reset0000000000000000
Reg Addr Base + 0x0010
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EEI47 EEI46 EEI45 EEI44 EEI43 EEI42 EEI41 EEI40 EEI39 EEI38 EEI37 EEI36 EEI35 EEI34 EEI33 EEI32
W
Reset0000000000000000
Reg Addr Base + 0x0010
Figure 9-6. eDMA Enable Error Interrupt High Register (EDMA_EEIRH)—MPC5554 Only
0123456789101112131415
R EEI31 EEI30 EEI29 EEI28 EEI27 EEI26 EEI25 EEI24 EEI23 EEI22 EEI21 EEI20 EEI19 EEI18 EEI17 EEI16
W
Reset0000000000000000
Reg Addr Base + 0x0014
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EEI15 EEI14 EEI13 EEI12 EEI11 EEI10 EEI09 EEI08 EEI07 EEI06 EEI05 EEI04 EEI03 EEI02 EEI01 EEI00
W
Reset0000000000000000
Reg Addr Base + 0x0014
Figure 9-7. eDMA Enable Error Interrupt Low Register (EDMA_EEIRL)
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