MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 12-27
The data transfer phase performs the transfer of data, from master to slave (in write cycles) or from slave
to master (on read cycles), if any is to be transferred. The data phase may transfer a single beat of data (1-4
bytes) for non-burst operations or a 2-beat (special EBI_MCR[DBM]=1 case only), 4-beat, 8-beat, or
16-beat burst of data (2 or 4 bytes per beat depending on port size) when burst is enabled. On a write cycle,
the master must not drive write data until after the address transfer phase is complete. This is to avoid
electrical contentions when switching between drivers. The master must start driving write data one cycle
after the address transfer cycle. The master can stop driving the data bus as soon as it samples the TA line
asserted on the rising edge of CLKOUT. To facilitate asynchronous write support, the EBI keeps driving
valid write data on the data bus until 1 clock after the rising edge where RD_WR (and WE for chip select
accesses) are negated.
See Figure 12-14 for an example of write timing. On a read cycle, the master accepts the data bus contents
as valid on the rising edge of the CLKOUT in which the TA signal is sampled asserted. See Figure 12-10
for an example of read timing.
The termination phase is where the cycle is terminated by the assertion of either TA (normal termination)
or TEA (termination with error). Termination is discussed in detail in Section 12.4.2.9, “Termination
Signals Protocol.”
12.4.2.4 Single Beat Transfer
The flow and timing diagrams in this section assume that the EBI is configured in single master mode.
Therefore, arbitration is not needed and is not shown in these diagrams. Refer to Section 12.4.2.10, “Bus
Operation in External Master Mode,” to see how the flow and timing diagrams change for external master
mode.
12.4.2.4.1 Single Beat Read Flow
The handshakes for a single beat read cycle are illustrated in the following flow and timing diagrams.
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