MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 12-31
Figure 12-14. Single Beat 32-bit Write Cycle, CS Access, Zero Wait States
Figure 12-15. Single Beat 32-bit Write Cycle, CS
Access, One Wait State
00
DATA is valid
CLKOUT
ADDR[8:31]
TS
DATA[0:31]
TA
RD_WR
TSIZ[0:1]
BDIP
WE[0:3]
CS
x
Wait state
DATA is valid
00
CLKOUT
ADDR[8:31]
TS
DATA[0:31]
TA
RD_WR
TSIZ[0:1]
BDIP
WE[0:3]
CS
x