MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 17-27
Note that for input modes, any input events that may occur while the channel is frozen are ignored.
When exiting debug mode or freeze enable bit is cleared (FRZ in the EMIOS_MCR or FREN in the
EMIOS_CCRn) the channel actions resume.
17.4.4.4 Modes of Operation of the Unified Channels
The mode of operation of a unified channel is determined by the mode select bits MODE[0:6] in the
EMIOS_CCRn. See Table 17-11 for details.
When entering an output mode (except for GPIO mode), the output flip-flop is set to the complement of
the EDPOL bit in the EMIOS_CCRn.
Because the internal counter EMIOS_CCNTRn continues to run in all modes (except for GPIO mode), it
is possible to use this counter as the UC time base unless it (the internal counter) is a required resource in
the operation of the selected mode.
To provide smooth waveform generation while allowing A and B registers to be asynchronously updated
during UC operation, the double-buffered modes MCB, OPWFMB, OPWMB, and OPWMCB are
provided (beginning at Section 17.4.4.4.15, “Modulus Counter, Buffered Mode (MCB) (MPC5553
Only)”). In these modes the A and B registers are double buffered. Descriptions of the double-buffered
modes are presented separately, because there are several basic differences from the single-buffered MC,
OPWFM, OPWM, and OPWMC modes.
Section 17.4.4.4.2, “Single Action Input Capture Mode (SAIC)” through Section 17.4.4.4.18, “Output
Pulse Width Modulation, Buffered Mode (OPWMB) (MPC5553 Only)” below explain in detail the unified
channels’ modes of operation.
17.4.4.4.1 General Purpose Input/Output Mode (GPIO)
In GPIO mode, all input capture and output compare functions of the UC are disabled, the internal counter
(EMIOS_CCNTRn register) is cleared and disabled. All control bits remain accessible. In order to prepare
the UC for a new operating mode, writing to registers EMIOS_CADRn or EMIOS_CBDRn stores the
same value in registers A1/A2 or B1/B2, respectively.
MODE[6] bit selects between input (MODE[6] = 0) and output (MODE[6] = 1) modes.
It is required that when changing MODE[0:6], the application software goes to GPIO mode first in order
to reset the UC’s internal functions properly. Failure to do this can lead to invalid and unexpected output
compares and input capture results, or can cause the FLAGs to be set incorrectly.
In GPIO input mode, the FLAG generation is determined according to EDPOL and EDSEL bits and the
input pin status can be determined by reading the UCIN bit.
In GPIO output mode, the unified channel is used as a single output port pin and the value of the EDPOL
bit is permanently transferred to the output flip-flop.
Table 17-14. Mode of Operation: GPIO Mode
MODE[0:6] Unified Channel Mode of Operation
0b0000000 General purpose input/output mode (input)
0b0000001 General purpose input/output mode (output)
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