MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 17-33
17.4.4.4.7 Pulse/Edge Accumulation Mode (PEA)
The PEA mode returns the time taken to detect a desired number of input events. MODE[6] bit selects
between continuous or single shot operation.
After writing to register A1, the internal counter is cleared on the first input event, ready to start counting
input events and the selected timebase is latched into register B2. On the match between the internal
counter and register A1, a counter bus capture is triggered to register A2 and B2. The data previously held
in register B2 is transferred to register B1 and the FLAG bit is set to indicate that an event has occurred.
The desired time interval can be determined subtracting register B1 from A2. Registers EMIOS_CADRn
and EMIOS_CBDRn return the values in register A2 and B1, respectively.
In order to guarantee coherent access, reading EMIOS_CADRn disables transfers between B2 and B1 until
reading EMIOS_CBDRn register, then any pending transfer is re-enabled.
Triggering of the counter clock (input event) is done by a rising or falling edge or both edges on the input
pin. The polarity of the triggering edge is selected by the EDSEL and EDPOL bits in EMIOS_CCRn.
For continuous operating mode (MODE[6] cleared), the counter is cleared on the next input event after a
FLAG generation and continues to operate as described above.
For single shot operation (MODE[6] set), the counter is not cleared or incremented after a FLAG
generation, until a new writing operation to register A is performed.
NOTE
The FORCMA and FORCMB bits have no effect when the unified channel
is configured for PEA mode.
Figure 17-22 and Figure 17-23 show how the unified channel can be used for continuous and single shot
pulse/edge accumulation mode.
Table 17-20. Mode of Operation: PEA Mode
MODE[0:6] Unified Channel Mode of Operation
0b0001000 Pulse/edge accumulation (continuous)
0b0001001 Pulse/edge accumulation (single shot)
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