Freescale Semiconductor MPC5553 - Page 671

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
17-32 Freescale Semiconductor
At any time, the EMIOS_CCRn[FORCMA] and EMIOS_CCRn[FORCMB] bits allow the software to
force the output flip-flop to the level corresponding to a comparison event in comparator A or B,
respectively. Note that the FLAG bit is not affected by these forced operations.
NOTE
If both registers (A1 and B1) are loaded with the same value, the unified
channel behaves as if a single match on comparator B had occurred; that is,
the output flip-flop will be set to the complement of EDPOL bit and the
FLAG bit is set.
Figure 17-20 and Figure 17-21 show how the unified channel can be used to generate a single output pulse
with FLAG bit being set on the second match or on both matches, respectively.
Figure 17-20. Double Action Output Compare with FLAG Set on the Second Match
Figure 17-21. Double Action Output Compare with FLAG Set on Both Matches
Selected
Counter Bus
FLAG
Set Event
A1 Match
0xxxxxxx 0x001000 0x001000 0x001000
Notes:
1
Writing EMIOS_CADRn writes to A1.
2
Writing EMIOS_CBDRn writes to B1.
MODE[6] = 0
B1 Match B1 Match
0xxxxxxx 0x001100 0x0011000x001100
A1 Match
Update to
A1 & B1
Output
Flip-Flop
A1 Value
1
B1 Value
2
A2value transferred to A1 according to OUn bit.
B2value transferred to B1 according to OUn bit.
0x000500 0x001000 0x001100 0x001000 0x001100
Selected
Counter Bus
FLAG
Set Event
A1 Match
0xxxxxxx 0x001000 0x001000 0x001000
Notes:
1
Writing EMIOS_CADRn writes to A1.
2
Writing EMIOS_CBDRn writes to B1.
MODE[6] = 1
B1 Match B1 Match
0xxxxxxx 0x001100 0x0011000x001100
A1 Match
Update to
A1 & B1
Output
Flip-Flop
A1 Value
1
B1 Value
2
A2value transferred to A1 according to OUn bit.
B2value transferred to B1 according to OUn bit.
0x000500 0x001000 0x001100 0x001000 0x001100