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Touch sensing controller (TSC) RM0091

692/742 Doc ID 018940 Rev 1

Bit 1 START: Start a new acquisition

This bit is set by software to start a new acquisition. It is cleared by hardware as soon as the

acquisition is complete or by software to cancel the on-going acquisition.

0: Acquisition not started

1: Start a new acquisition

Bit 0 TSCE: Touch sensing controller enable

This bit is set and cleared by software to enable/disable the touch sensing controller.

0: Touch sensing controller disabled

1: Touch sensing controller enabled

Note: When the touch sensing controller is disabled, TSC registers settings have no effect.

Default Chapter1
- Table 1. Applicable Products1
  - Table of Contents2
  - SYSCFG External Interrupt Configuration Register4
Documentation Conventions34
- List of Abbreviations for Registers34
- Glossary34
- Peripheral Availability34
System and Memory Overview35
- System Architecture35
- Figure 1. System Architecture35
- Memory Organization37
- Embedded SRAM40
- Flash Memory Overview40
- Boot Configuration40
- Table 3. Boot Modes40
Embedded Flash Memory42
- Flash Main Features42
- Flash Memory Functional Description42
- Memory Protection49
- Flash Interrupts52
- Flash Register Description52
- Flash Register Map58
- Table 8. Flash Interface - Register Map and Reset Values58
Option Byte Description59
- Table 9. Option Byte Format59
- Table 10. Option Byte Organization59
- Table 11. Description of the Option Bytes60
Cyclic Redundancy Check Calculation Unit (CRC)62
- Introduction62
- CRC Main Features62
- CRC Functional Description63
- Figure 5. CRC Calculation Unit Block Diagram63
- CRC Registers64
Power Control (PWR)67
- Power Supplies67
- Power Supply Supervisor69
- Low-Power Modes71
- Power Control Registers77
Reset and Clock Control (RCC)82
- Reset82
- Clocks83
- Low Power Modes90
- RCC Registers92
General-Purpose I/Os (GPIO)118
- GPIO Introduction118
- GPIO Main Features118
- GPIO Functional Description118
- GPIO Registers127
System Configuration Controller (SYSCFG)135
- SYSCFG Registers135
Direct Memory Access Controller (DMA)142
- DMA Introduction142
- DMA Main Features142
- DMA Functional Description143
- DMA Registers150
Interrupts and Events157
- Nested Vectored Interrupt Controller (NVIC)157
- Extended Interrupts and Events Controller (EXTI)159
- EXTI Registers163
Analog-To-Digital Converter (ADC)168
- Introduction168
- ADC Main Features169
- ADC Pins and Internal Signals170
- Table 29. ADC Internal Signals170
- Table 30. ADC Pins170
- ADC Functional Description171
- Conversion on External Trigger and Trigger Polarity (EXTSEL, EXTEN)178
- Data Management183
- Low Power Features185
- Analog Window Watchdog187
- Temperature Sensor and Internal Reference Voltage189
- Figure 37. Temperature Sensor and VREFINT Channel Block Diagram189
- Battery Voltage Monitoring190
- ADC Interrupts191
- Table 37. ADC Interrupts191
- ADC Registers192
Digital-To-Analog Converter (DAC1)205
- DAC1 Introduction205
- DAC1 Main Features205
- Single Mode Functional Description206
- DMA Request209
- DAC Registers209
Comparator (COMP)215
- COMP Introduction215
- COMP Main Features215
- COMP Functional Description216
- COMP Registers219
Advanced-Control Timers (TIM1)223
- TIM1 Introduction223
- TIM1 Main Features223
- Figure 43. Advanced-Control Timer Block Diagram224
- TIM1 Functional Description225
- TIM1 Registers265
General-Purpose Timers (TIM2 and TIM3)292
- TIM2 and TIM3 Introduction292
- TIM2 and TIM3 Main Features292
- TIM2 and TIM3 Functional Description293
- TIM2 and TIM3 Registers329
General-Purpose Timer (TIM14)353
- TIM14 Introduction353
- TIM14 Main Features353
- TIM14 Functional Description354
- TIM14 Registers365
General-Purpose Timers (TIM15/16/17)375
- TIM15/16/17 Introduction375
- TIM15 Main Features375
- TIM16 and TIM17 Main Features376
- Figure 152. TIM15 Block Diagram377
- Figure 153. TIM16 and TIM17 Block Diagram378
- TIM15/16/17 Functional Description379
- TIM15 Registers402
- TIM16 and TIM17 Registers422
Basic Timer (TIM6)440
- TIM6 Introduction440
- TIM6 Main Features440
- Figure 181. Basic Timer Block Diagram440
- TIM6 Functional Description441
- TIM6 Registers447
Infrared (IRTIM) Interface452
- Main Features452
- Figure 191. IR Internal Hardware Connections with TIM16 and TIM17452
Independent Watchdog (IWDG)453
- Introduction453
- IWDG Main Features453
- IWDG Functional Description453
- IWDG Registers455
System Window Watchdog (WWDG)461
- WWDG Introduction461
- WWDG Main Features461
- WWDG Functional Description461
- Figure 193. Watchdog Block Diagram462
- How to Program the Watchdog Timeout463
- Figure 194. Window Watchdog Timing Diagram463
- Debug Mode464
- WWDG Registers465
Inter-Integrated Circuit (I 2 C) Interface468
- I 2 C Introduction468
- I 2 C Main Features468
- Table 61. I2C Configurations in Goldfish and Manta Edge468
- I2C Implementation469
- I 2 C Functional Description469
- I 2 C Interrupts517
- Table 75. I2C Interrupt Requests517
- Figure 226. I2C Interrupt Mapping Diagram518
- I 2 C Debug Mode519
- I 2 C Registers519
- I2C Register Map534
- Table 76. I2C Register Map and Reset Values534
Real-Time Clock (RTC)535
- Introduction535
- RTC Main Features535
- RTC Functional Description536
- RTC Low Power Modes548
- Table 80. Effect of Low Power Modes on RTC548
- RTC Interrupts549
- Table 81. Interrupt Control Bits549
- RTC Registers550
Universal Synchronous Asynchronous Receiver Transmitter (USART)571
- USART Introduction571
- USART Main Features571
- USART Extended Features572
- USART Implementation573
- USART Functional Description573
- USART Interrupts609
- Table 89. USART Interrupt Requests609
- Figure 252. USART Interrupt Mapping Diagram610
- USART Registers611
Serial Peripheral Interface / Inter-IC Sound (SPI/I2S)634
- Introduction634
- SPI/I2S Implementation635
- SPI Functional Description635
- SPI Special Features648
- SPI Interrupts652
- S Functional Description652
- SPI and I 2 S Registers670
Touch Sensing Controller (TSC)681
- Introduction681
- TSC Main Features681
- TSC Functional Description682
- TSC Low Power Modes689
- TSC Interrupts689
- Table 98. Capacitive Sensing Gpios Available on Stm32F05Xxx Devices689
- Table 99. Effect of Low Power Modes on TSC689
- Table 100. Interrupt Control Bits689
- TSC Registers690
HDMI-CEC Controller (HDMI-CEC)699
- Introduction699
- HDMI-CEC Controller Main Features699
- HDMI-CEC Functional Description700
- Arbitration702
- Error Handling704
- HDMI-CEC Interrupts708
- Table 105. HDMI-CEC Interrupts708
- HDMI-CEC Registers709
Debug Support (DBG)718
- Overview718
- Reference ARM Documentation719
- Pinout and Debug Port Pins719
- ID Codes and Locking Mechanism720
  - Table 107. SW Debug Port Pins720
  - MCU Device ID Code721
- SW Debug Port721
- Core Debug725
- Table 112. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]725
- Table 113. Core Debug Registers725
- BPU (Break Point Unit)726
  - BPU Functionality726
- DWT (Data Watchpoint)726
  - DWT Functionality726
  - DWT Program Counter Sample Register726
- MCU Debug Component (DBGMCU)726
Device Electronic Signature733
- Unique Device ID Register (96 Bits)733
- Memory Size Data Register735
  - Flash Size Data Register735
Revision History741
- Table 115. Document Revision History741

Brand	STMicroelectronics
Model	STM32F05 series
Category	Microcontrollers
Language	English

STMicroelectronics STM32F05 series User Manual

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