MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 3-17
The MAS2 register is shown in Figure 3-9.
MAS2 fields are defined in Table 3-5.
Table 3-4. MAS1 —Descriptor Context and Configuration Control
Bits Name Description
0 VALID TLB entry valid
0 This TLB entry is invalid.
1 This TLB entry is valid.
1 IPROT Invalidation protect
0 Entry is not protected from invalidation.
1 Entry is protected from invalidation.
Protects TLB entry from invalidation by tlbivax (TLB1 only), or flash invalidates through
MMUCSR0[TLB1_FI].
2–7 — Reserved, should be cleared.
8–15 TID Translation ID bits
This field is compared with the current process IDs of the effective address to be translated. A TID
value of 0 defines an entry as global and matches with all process IDs.
16–18 — Reserved, should be cleared.
19 TS Translation address space
This bit is compared with the IS or DS fields of the MSR (depending on the type of access) to
determine if this TLB entry may be used for translation.
20–23 TSIZE Entry page size
Supported page sizes are:
0b00014 Kbytes 0b01104 Mbytes
0b001016 Kbytes 0b011116 Mbytes
0b001164 Kbytes 0b100064 Mbytes
0b0100256 Kbytes 0b1001256 Mbytes
0b01011 Mbyte
All other values are undefined.
24–31 — Reserved, should be cleared.
0 1920 262728293031
Field EPN — W I M G E
Reset Undefined on Power Up Unchanged on Reset
R/W R/W
SPR SPR 626
Figure 3-9. MMU Assist Register 2 (MAS2)
Table 3-5. MAS2—EPN and Page Attributes
Bits Name Description
0–19 EPN Effective page number
20–26 — Reserved, should be cleared.
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