MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
12-60 Freescale Semiconductor
Figure 12-42. External Master Write to MCU
12.4.2.10.3 Bus Transfers Initiated by the EBI in External Master Mode
The flow and timing for EBI-mastered transactions in external master mode is identical to that described
in earlier sections for single master mode, with the exception that the EBI must now arbitrate for the bus
before each transaction. The flow and timing diagrams below show the arbitration sequence added to
Figure 12-9 and Figure 12-10 for the basic single beat read case. The remaining cases (writes, bursts, etc.)
can be obtained by adding the arbitration sequence to the flow and timing diagrams shown for single
master mode in earlier sections. See Section 12.4.2.4, “Single Beat Transfer,” and Section 12.4.2.5, “Burst
Transfer.”
If the external master is another MCU with this EBI, then BB and other control pins are turned off
*
If the external master is another MCU with this EBI, then DATA remains valid as shown due to use
of latched TA
internally. These extra data valid cycles (past TA) are not required by the slave EBI.
**
as shown due to use of latched TA internally. This extra cycle is not required by the slave EBI.
Receive bus grant and bus busy
negated for 2nd cycle
Assert BB drive address
and assert TS
Using the internal arbiter
CLKOUT
BR (Input)
RD_WR
TSIZ[0:1]
BDIP
BG
BB
ADDR[8:31]
DATA[0:31]
TS
(Input)
Minimum
2 wait states
DATA is valid
TA
(Output)
*
DATA is valid
**
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