MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
14-26 Freescale Semiconductor
14.3.4.2.14 Descriptor Individual Upper Address Register (IAUR)
The IAUR is written by the user. This register contains the upper 32 bits of the 64-bit individual address
hash table used in the address recognition process to check for possible match with the DA field of receive
frames with an individual DA. This register is not reset and must be initialized by the user.
0 12 3 4 5 6 7 8 9101112131415
R IADDR1
W
ResetUUUUUUUUUUUUUUU U
Address Base + 0x0118
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R IADDR1
W
ResetUUUUUUUUUUUUUUU U
Address Base + 0x0118
1
“U” signifies a bit that is uninitialized.
Figure 14-16. Descriptor Individual Upper Address Register (IAUR)
Table 14-19. IAUR Field Descriptions
Bits Name Descriptions
0–31 IADDR1 The upper 32 bits of the 64-bit hash table used in the address recognition
process for receive frames with a unicast address. Bit 31 of IADDR1
contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
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