MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 14-27
14.3.4.2.15 Descriptor Individual Lower Address (IALR)
The IALR register is written by the user. This register contains the lower 32 bits of the 64-bit individual
address hash table used in the address recognition process to check for possible match with the DA field
of receive frames with an individual DA. This register is not reset and must be initialized by the user.
0 12 3 4 5 6 7 8 9101112131415
R IADDR2
W
ResetUUUUUUUUUUUUUUU U
Address Base + 0x011C
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R IADDR2
W
ResetUUUUUUUUUUUUUUU U
Address Base + 0x011C
1
“U” signifies a bit that is uninitialized.
Figure 14-17. Descriptor Individual Lower Address Register (IALR)
Table 14-20. IALR Field Descriptions
Bits Name Description
0–31 IADDR2 The lower 32 bits of the 64-bit hash table used in the address recognition
process for receive frames with a unicast address. Bit 31 of IADDR2 contains
hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
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