MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
14-28 Freescale Semiconductor
14.3.4.2.16 Descriptor Group Upper Address (GAUR)
The GAUR is written by the user. This register contains the upper 32 bits of the 64-bit hash table used in
the address recognition process for receive frames with a multicast address. This register must be
initialized by the user.
0 12 3 4 5 6 7 8 9101112131415
R GADDR1
W
ResetUUUUUUUUUUUUUUU U
Address Base + 0x0120
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R GADDR1
W
ResetUUUUUUUUUUUUUUU U
Address Base + 0x0120
1
“U” signifies a bit that is uninitialized.
Figure 14-18. Descriptor Group Upper Address Register (GAUR)
Table 14-21. GAUR Field Descriptions
Bits Name Description
0–31 GADDR1 The GADDR1 register contains the upper 32 bits of the 64-bit hash table used
in the address recognition process for receive frames with a multicast
address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of GADDR1
contains hash index bit 32.
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