MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
17-10 Freescale Semiconductor
17.3.1.2 eMIOS Global Flag Register (EMIOS_GFR)
The EMIOS_GFR is a read-only register that groups the FLAG bits from all channels. This organization
improves interrupt handling on simpler devices. These bits are mirrors of the FLAG bits of each channel
register (EMIOS_CSR) and flag bits in those channel registers cannot be cleared by accessing this ‘mirror’
register.
17.3.1.3 eMIOS Output Update Disable Register (EMIOS_OUDR)
The EMIOS_OUDR serves to disable transfers from the A2 to the A1 channel registers and from the B2
to the B1 channel registers when values are written to these registers, and the channel is running in
modulus counter (MC) mode or an output mode.
Table 17-7. Global Prescaler Clock Divider
GPRE[0:7] Divide Ratio
00000000 1
00000001 2
.
.
.
.
.
.
.
.
11111111 256
0123456789101112131415
R00000000F23F22F21F20F19F18F17F16
W
Reset0000000000000000
Reg Addr Base + 0x0004
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RF15F14F13F12F11F10F9F8F7F6F5F4F3F2F1F0
W
Reset0000000000000000
Reg Addr Base + 0x0004
Figure 17-3. eMIOS Global Flag Register (EMIOS_GFR)
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