MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
20-16 Freescale Semiconductor
16–19 CSSCK
[0:3]
PCS to SCK delay scaler. Selects the scaler value for the PCS to SCK delay. This field
is only used in master mode. The PCS to SCK delay is the delay between the assertion
of PCS and the first edge of the SCK. The table below lists the scaler values.
The PCS to SCK delay is a multiple of the system clock period and it is computed
according to the following equation:
Note: See Section 20.4.6.2, “PCS to SCK Delay (tCSC),” for more details.
Table 20-5. DSPIx_CTARn Field Description (Continued)
Bits Name Description
CSSCK
PCS to SCK Delay
Scaler Value
CSSCK
PCS to SCK Delay
Scaler Value
0000 2 1000 512
0001 4 1001 1024
0010 8 1010 2048
0011 16 1011 4096
0100 32 1100 8192
0101 64 1101 16384
0110 128 1110 32768
0111 256 1111 65536
t
CSC
1
f
SYS
-----------
PCSSCK Prescaler value CSSCK Scaler value=
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