GigaDevice Semiconductor GD32F3x0 - Page 221

GD32F3x0 User Manual
221
reaches 0x40. It can be cleared by a hardware reset or software reset by setting
the WWDGTRST bit of the RCU module. A write of 0 has no effect.
8:7
PSC[1:0]
Prescaler. The time base of the watchdog counter
00: PCLK1 / 4096 / 1
01: PCLK1 / 4096 / 2
10: PCLK1 / 4096 / 4
11: PCLK1 / 4096 / 8
6:0
WIN[6:0]
The Window value. A reset will occur if the watchdog counter (CNT bits in
WWDGT_CTL) is written when the value of the watchdog counter is greater than
the Window value.
Status register (WWDGT_STAT)
Address offset: 0x08
Reset value: 0x0000 0000
This register can be accessed by half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
EWIF
rw
Bits
Fields
Descriptions
31:1
Reserved
Must be kept at reset value.
0
EWIF
Early wakeup interrupt flag. When the counter reaches 0x40, this bit is set by
hardware even the interrupt is not enabled (EWIE in WWDGT_CFG is cleared).
This bit is cleared by writing 0 to it. There is no effect when writing 1 to it.