GD32F3x0 User Manual
258
Counter center-aligned counting
In this mode, the counter counts up from 0 to the counter-reload value and then counts down
to 0 alternatively. The Timer module generates an overflow event when the counter counts to
the counter-reload value subtract 1 in the up-counting direction and generates an underflow
event when the counter counts to 1 in the down-counting direction. The counting direction bit
DIR in the TIMERx_CTL0 register is read-only and indicates the counting direction when in
the center-aligned mode.
Setting the UPG bit in the TIMERx_SWEVG register will initialize the counter value to 0 and
generates an update event irrespective of whether the counter is counting up or down in the
center-align counting mode.
The UPIF bit in the TIMERx_INTF register can be set to 1 either when an underflow event or
an overflow event occurs. While the CHxIF bit is associated with the value of CAM in
TIMERx_CTL0. The details refer to Figure 16-8. Timing chart of center-aligned counting
mode.
If set the UPDIS bit in the TIMERx_CTL0 register, the update event is disabled.
When an update event occurs, all the shadow registers (repetition counter, counter
auto-reload register, prescaler register) are updated.
Figure 16-8. Timing chart of center-aligned counting mode show some examples of the
counter behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0
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