GigaDevice Semiconductor GD32F3x0 - Page 472

GD32F3x0 User Manual
472
1: RTS hardware flow control enabled, data can be requested only when there is
space in the receive buffer.
This bit field cannot be written when the USART is enabled (UEN=1).
7
DENT
DMA enable for transmission
0: DMA mode is disabled for transmission.
1: DMA mode is enabled for transmission.
6
DENR
DMA enable for reception
0: DMA mode is disabled for reception
1: DMA mode is enabled for reception
5
SCEN
Smartcard mode enable
0: Smartcard mode disabled
1: Smartcard mode enabled
This bit field cannot be written when the USART is enabled (UEN=1).
This bit is reserved in USART1.
4
NKEN
NACK enable in Smartcard mode
0: Disable NACK transmission when parity error.
1: Enable NACK transmission when parity error.
This bit field cannot be written when the USART is enabled (UEN=1).
This bit is reserved in USART1.
3
HDEN
Half-duplex enable
0: Half duplex mode is disabled.
1: Half duplex mode is enabled.
This bit field cannot be written when the USART is enabled (UEN=1).
2
IRLP
IrDA low-power
0: Normal mode
1: Low-power mode
This bit field cannot be written when the USART is enabled (UEN=1).
1
IREN
IrDA mode enable
0: IrDA disabled
1: IrDA enabled
This bit field cannot be written when the USART is enabled (UEN=1).
This bit is reserved in USART1.
0
ERRIE
Error interrupt enable
0: Error interrupt disabled.
1: An interrupt will occur whenever the FERR bit or the ORERR bit or the NERR bit
is set in USART_STAT in multibuffer communication.
18.4.4. Baud rate generator register (USART_BAUD)
Address offset: 0x0C