GigaDevice Semiconductor GD32F3x0 - Page 474

GD32F3x0 User Manual
474
00000001: divides the source clock by 1.
00000010: divides the source clock by 2.
...
In IrDA normal mode,
00000001: can be set this value only
In smartcard mode, the prescaler value for dividing the system clock is stored in
PSC[4:0] bits. And the bits of PSC[7:5] must be kept at reset value. The division
factor is twice as the prescaler value.
00000: Reserved - do not program this value.
00001: divides the source clock by 2.
00010: divides the source clock by 4.
00011: divides the source clock by 6.
...
This bit field cannot be written when the USART is enabled (UEN=1).
18.4.6. Receiver timeout register (USART_RT)
Address offset: 0x14
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
This bit is reserved in USART1.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BL[7:0]
RT[23:16]
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RT[15:0]
rw
Bits
Fields
Descriptions
31:24
BL[7:0]
Block Length
These bits specify the block length in smartcard T=1 reception. Its value equals the
number of information characters + the length of the Epilogue Field (1-LEC/2-CRC)
- 1.
This value, which must be programmed only once per received block, can be
programmed after the start of the block reception (using the data from the LEN
character in the Prologue Field). The block length counter is reset when TBE=0 in
smartcard mode.
In other modes, when REN=0 (receiver disabled) and/or when the EBC bit is
written to 1, the block length counter is reset.
23:0
RT[23:0]
Receiver timeout threshold
These bits are used to specify receiver timeout value in terms of number of baud
clocks.