GD32F3x0 User Manual
491
I2C_STAT1.
5. Now I2C enters data transmission stage and hardware sets TBE bit because both the
shift register and data register I2C_DATA are empty. Software now writes the first byte
data to I2C_DATA register, but the TBE will not be cleared because the byte written in
I2C_DATA is moved to internal shift register immediately. The I2C begins to transmit
data to I2C bus as soon as the shift register is not empty.
6. During the transmission of the first byte, software can write the second byte to
I2C_DATA, and this time TBE is cleared because neither I2C_DATA nor shift register is
empty.
7. Any time TBE is set, software can write a byte to I2C_DATA as long as there is still data
to be transmitted.
8. During the transmission of the second last byte, software writes the last data to
I2C_DATA to clear the TBE flag and doesn’t care TBE anymore. So TBE will be
asserted after the transmission of the byte and not be cleared until a STOP signal.
9. After sending the last byte, I2C master sets BTC bit because both the shift register and
I2C_DATA are empty. Software should set the STOP bit to generate a STOP signal,
then the I2C clears both TBE and BTC flags.
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