GigaDevice Semiconductor GD32F3x0 - Page 545

GD32F3x0 User Manual
545
1
CKPL
Clock polarity selection
0: CLK pin is pulled low when SPI is idle.
1: CLK pin is pulled high when SPI is idle.
0
CKPH
Clock phase selection
0: Capture the first data at the first clock transition.
1: Capture the first data at the second clock transition.
20.5.2. Control register 1 (SPI_CTL1)
Address offset: 0x04
Reset value: 0x0000 0000
This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
TBEIE
RBNEIE
ERRIE
TMOD
NSSP
NSSDRV
DMATEN
DMAREN
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:8
Reserved
Must be kept at reset value.
7
TBEIE
Transmit buffer empty interrupt enable
0: Disable TBE interrupt
1: Enable TBE interrupt. An interrupt is generated when the TBE bit is set.
6
RBNEIE
Receive buffer not empty interrupt enable
0: Disable RBNE interrupt
1: Enable RBNE interrupt. An interrupt is generated when the RBNE bit is set.
5
ERRIE
Errors interrupt enable.
0: Disable error interrupt
1: Enable error interrupt. An interrupt is generated when the CRCERR bit or the
CONFERR bit or the FERR bit or the RXORERR bit or the TXURERR bit is set.
4
TMOD
SPI TI mode enable.
0: Disable SPI TI mode
1: Enable SPI TI mode
3
NSSP
SPI NSS pulse mode enable.
0: Disable SPI NSS pulse mode
1: Enable SPI NSS pulse mode
2
NSSDRV
Drive NSS output
0: Disable master NSS output