GigaDevice Semiconductor GD32F3x0 - Page 552

GD32F3x0 User Manual
552
This bit is not used in SPI mode.
8
OF
Odd factor for the prescaler
0: Real divider value is DIV * 2
1: Real divider value is DIV * 2 + 1
This bit should be configured when I2S mode is disabled.
This bit is not used in SPI mode.
7:0
DIV[7:0]
Dividing factor for the prescaler
Real divider value is DIV * 2 + OF.
DIV must not be 0.
These bits should be configured when I2S mode is disabled.
These bits are not used in SPI mode.
20.5.10. Quad-SPI mode control register (SPI_QCTL) of SPI1
Address offset: 0x80
Reset value: 0x0000 0000
This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
IO23_DR
V
QRD
QMOD
rw
rw
rw
Bits
Fields
Descriptions
31:3
Reserved
Must be kept at reset value.
2
IO23_DRV
Drive IO2 and IO3 enable
0: IO2 and IO3 are not driven in single wire mode.
1: IO2 and IO3 are driven to high in single wire mode.
This bit is only available in SPI1.
1
QRD
Quad-SPI mode read select.
0: SPI is in quad wire write mode.
1: SPI is in quad wire read mode.
This bit can only be configured when the SPI is not busy (the TRANS bit is
cleared).
This bit is only available in SPI1.
0
QMOD
Quad-SPI mode enable.
0: SPI is in single wire mode.
1: SPI is in Quad-SPI mode.
This bit can only be configured when the SPI is not busy (the TRANS bit is