GigaDevice Semiconductor GD32F3x0 - Page 583

GD32F3x0 User Manual
583
0: MNERR interrupt is disabled
1: MNERR interrupt is enabled
0
CTCFIE
Charge-transfer complete flag Interrupt Enable
0: CTCF interrupt is disabled
1: CTCF interrupt is enabled
22.4.3. Interrupt flag clear register (TSI_INTC)
Address offset: 0x08
Reset value: 0x0000 0000
This register can be accessed by word(32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CMNERR
CCTCF
w
w
Bits
Fields
Descriptions
31:2
Reserved
Must be kept at reset value
1
CMNERR
Clear max cycle number error
0: Reserved
1: Clear MNERR
0
CCTCF
Clear charge-transfer complete flag
0: Reserved
1: Clear CTCF
22.4.4. Interrupt flag register (TSI_INTF)
Address offset: 0x0C
Reset value: 0x0000 0000
This register can be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
MNERR
CTCF
r
r